1. Field of the Invention
The present invention relates generally to semiconductor memory devices having separate read and write buses, and more particularly, to an improved construction thereof and an operating method therefor, wherein access time for reading out data from the device is reduced to provide a high-speed operation.
2. Description of the Background Art
Recently, it has been desired in a highly integrated memory device such as a dynamic MOSRAM (Random Access Memory using MOS transistors) to achieve high integration density for increasing storage capacity thereof and to increase the speed of a reading operation by substantially reducing access time (time required for reading out data).
FIG. 1 is a diagram showing schematically an entire structure of a conventional semiconductor memory device. This semiconductor memory device is a dynamic random access memory (DRAM).
In FIG. 1, a memory cell array 101 comprises a plurality of memory cells arranged in of rows and columns so as to have a folded bit line structure. An address buffer 102 generates an internal row address signal and an internal column address signal upon receipt of an externally applied address signal ADD. A row decoder 103 is responsive to the internal row address signal from the address buffer 102 for selecting the memory cells in one row out of the memory cell array 101. The column decoder 104 is responsive to the internal column address signal from the address buffer 102 for selecting the memory cells in one column (a single bit line pair) out of the memory cell array 101. A block 105 (including a sense amplifier portion and an I/O portion) amplifies a potential difference between signals on the bit line pair, and connects the selected bit line pair to a data input/output line in response to a column decoded signal from the column decoder 104. A write-in buffer 106 receives externally applied write data D.sub.IN for converting the received write data D.sub.IN into a set of complementary data (D.sub.IN , D.sub.IN) to transfer the same to the I/O portion in the block 105. A read-out buffer 107 receives the data from the I/O portion in the block 105 for outputting the same to the exterior as an output signal D.sub.OUT. A clock generator 108 generates signals such as a row address strobe signal RAS and a column address strobe signal CAS for providing timing of initiating a memory cycle and timing of accepting an address signal.
The row address strobe signal RAS from the clock generator 108 is applied to the address buffer 102, the row decoder 103 and the like, while the column address strobe signal CAS is applied to the address buffer 102, the column decoder 104 and the like.
As shown in FIG. 2, the row address strobe signal RAS provides timing of accepting the row address signal in the address buffer 102, while the column address strobe signal CAS provides timing of accepting the column address signal in the address buffer 102. The row address signal and the column address signal are applied to the address buffer 102 in a time series. In addition, timing of decoding the address signal in the row decoder 103 and timing of decoding the address signal in the column decoder 104 are respectively provided by the row address strobe signal RAS and the column address strobe signal CAS.
FIG. 3 is a diagram showing a structure of a main part of the memory cell array shown in FIG. 1, showing specifically one example of a structure of a block 150 represented by a dotted line.
In FIG. 3, a bit line pair BL and BL having a folded bit line structure is typically shown. The bit lines BL and BL are paired with each other, to constitute a folded bit line pair. More specifically, complementary signals appear on the bit lines BL and BL. A plurality of word lines are provided in a direction perpendicularly intersecting with the bit lines BL and BL. In FIG. 3, only a single word line WL is typically shown. Memory cells are respectively provided at intersections of the word line and the bit lines, the memory cells being arranged in rows and columns. In FIG. 3, only a single memory cell 1 provided at the intersection of the bit line BL and the word line WL is typically shown. The memory cell 1 is of a single transistor/a single capacitor type, which comprises a memory capacitor CO for storing information and an N channel MIS (Metal Insulator Semiconductor) transistor Q0.
In order to differentially amplify a potential difference between signals on the bit line pair BL and BL, there are provided flip-flop type sense amplifiers 2 and 3. The sense amplifier 2 comprises N channel MIS transistors Q1 and Q2. The sense amplifier 2 is activated in response to a signal from sense amplifier activating means 4, to discharge the bit line on the lower potential side such that a potential thereon becomes a ground potential. The sense amplifier activating means 4 comprises an N channel MIS transistor Q5 which is turned on in response to a sense amplifier activation signal SO to connect a node N1 to the ground potential. The sense amplifier 3 comprises P channel MIS transistors Q3 and Q4. The sense amplifier 3 is activated in response to a signal from sense amplifier activating means 5, to charge the bit line on the higher potential side such that a potential thereon becomes a power-supply potential Vcc. The sense amplifier activating means 5 comprises a P channel MIS transistor Q6 which is turned on in response to a sense amplifier activation signal SO to connect a node N2 to the power-supply potential Vcc.
Equalizing/precharging means 6 precharges each of the bit lines BL and BL at a predetermined precharge potential V.sub.BL and equalizes the potentials on the bit lines BL and BL before initiation of and after termination of a memory cycle (i.e., at standby time). The precharge potential V.sub.BL is generally generated by an internal voltage generating circuit, which is set to a predetermined potential (for example, one-half of the power-supply potential Vcc, i.e., Vcc/2).
Additionally, N channel MIS transistors Q10 and Q11 which are turned on in response to a column decoded signal Y from the column decoder (see in FIG. 1) are connected between the bit line pair BL and BL and a data input/output line pair I/O and I/O. The data input/output line pair I/O and is generally precharged at a predetermined potential V'.sub.BL by N channel MIS transistors Q22 and Q23 which are turned or in response to a clock signal CLK. The data input/output line pair I/O and I/O exchanges data through input/output buffers.
FIG. 4 is a signal waveform diagram showing a reading operation of the conventional semiconductor memory device, the same signs as those shown in FIG. 3 representing the change in potential in the corresponding portions.
Before the time T1, an equalizing signal EQ is at a high level, an equalizing transistor Q7 and precharging transistors Q8 and Q9 are all in the on state, the bit lines BL and BL being precharged at a predetermined potential V.sub.BL.
At the time T1, when the equalizing signal EQ is lowered from a high level to a low level, the transistors Q7, Q8, and Q9 are all turned off, so that the bit lines BL and BL are rendered electrically floating. Consequently, a precharging/equalizing operation is terminated. At the time T2, when a single word line WL is selected in response to a row decoded signal from a row decoder, a potential on the word line WL is changed from a low level to a high level. Consequently, the transistor Q0 of the memory cell 1 connected to the word line WL is turned on, so that the memory capacitor CO is connected to the bit line BL. As a result, the change in potential corresponding to information stored in the memory cell 1 occurs on the bit line BL. When the memory cell 1 stores information "1", the potential on the bit line BL is raised only slightly, as compared with the precharge potential as represented by solid lines in FIG. 4, while the bit line BL is held at the precharge potential.
When a potential of a read-out signal on the bit line pair BL and BL becomes stable, the sense amplifier activation signals SO and SO respectively start to be raised and lowered, at the time T3. Consequently, the transistors Q5 and Q6 are turned on, so that the nodes N1 and N2 are respectively charged and discharged such that potentials thereof respectively become the ground potential and the power-supply potential Vcc. As a result, the flip-flop type sense amplifiers 2 and 3 are both activated, so that the bit line BL on the higher potential side out of the bit lines BL and BL is charged through the sense amplifier 3 such that the potential thereon becomes the power-supply potential Vcc, while the bit line BL on the lower potential side is discharged through the sense amplifier 2 such that the potential thereon becomes the ground potential. More specifically, a very small potential difference between the signals on the bit line pair BL and BL is amplified.
After an amplifying operation of the sense amplifiers 2 and 3, when the column decoded signal Y from the column decoder becomes a high level at the time T4, the transistors Q10 and Q11 are turned on, so that the potentials on the bit lines BL and BL are respectively transmitted to the data input/output lines I/O and I/O. The potentials transmitted to the data input/output lines I/O and are amplified by amplifying means such as a preamplifier (not shown) and then, transmitted to the exterior through data output buffers and external output terminals (not shown).
When the transfer of data to the external output terminals is terminated, the potential on the word line WL is changed from a high level to a low level at the time T5, and the column decoded signal Y is also changed from a high level to a low level. Consequently, the potentials on the data input/output line pair I/O and I/O are returned to the precharge potential.
Then, at the time T6, the sense amplifier activation signals SO and SO are respectively changed to a low level and a high level, so that the sense amplifiers 2 and 3 are both rendered inactive. On this occasion, the equalizing signal EQ also becomes a high level, so that the precharging/equalizing means 6 is activated. As a result, the bit lines BL and BL are precharged at a predetermined potential V.sub.BL and the potentials on the bit lines BL and BL are equalized. The foregoing is the outline of the data reading operation.
On the other hand, in the data writing operation, timing of a signal waveform is the same as that shown in FIG. 4, in which data flows in a direction opposite to that in the reading operation, i.e., in the direction from a read-out buffer to a selected memory cell through a data input/output line pair. More specifically, write-in data externally applied through a write-in buffer (not shown) is transferred to the data input/output line pair I/O and I/O in a complementary manner (for example, D.sub.IN and D.sub.IN). After an operation sequence from the time T1 to the time T3, when the column decoded signal Y is changed from a low level to a high level at the time T4, the transistors Q10 and Q11 are turned on, so that signal potentials on the data input/output lines I/O and I/O are transmitted to the selected memory cell. In the above described manner, writing is performed.
On this occasion, the sense amplifiers 2 and 3 are also activated at the time T3, and the potential difference between the signals which appear on the bit lines BL and BL by the change of the potential on the word line WL to a high level. However, the write-in data is transferred to the data input/output line pair I/O and I/O through the write-in buffer from the exterior. Thus, even if the signal level amplified by the sense amplifiers 2 and 3 is opposite to the signal potential level of the write-in data, the signal potential corresponding to the write-in data appears on the bit line pair BL and BL. Consequently, the write-in data is written into the selected memory cell through the transistor Q0 in the on state.
As described in the foregoing, in the construction of the conventional semiconductor memory device, data is read out and written through the same data input/output line pair I/O and I/O. Thus, even in reading out data, the bit line pair BL and BL is connected to the data input/output line pair I/O and I/O through the transistors Q10 and Q11. In order to read out data at high speed, it is preferable to connect the bit line pair to the data input/output line pair as fast as possible. However, in FIG. 4, when the bit line pair and the data input/output line pair are connected to each other in a period, for example, from the time T2 when the potential on the word line WL rises to the time T3 when a sensing operation is initiated by activation of the sense amplifiers 2 and 3, a load capacitance of the data input/output line pair is applied to the bit lines, so that the levels of the read-out signals on the bit lines are lowered. Consequently, the sense amplifiers can not perform a reliable sensing operation and a malfunction may occur. Thus, it is necessary to connect the bit line pair to the data input/output line pair after the sense amplifiers 2 and 3 are activated and the signal potentials on the bit line pair BL and BL become stable. The connection between the selected bit line pair and the data input/output line pair at the time of data reading can not be made before the time T3.
Therefore, the conventional semiconductor memory device has the disadvantage that there is a limit in increasing the speed of a reading operation and it is difficult to shorten access time. More specifically, in a structure in which data is read out and written using the same data input/output line pair, it is difficult to shorten access time in the data reading operation.
Watanabe et al. have proposed a DRAM having write and read data buses separately provided for the purpose of high-speed reading, in an article entitled "BiCMOS CIRCUIT TECHNOLOGY FOR HIGH SPEED DRAMs", '87 VLSI SYMPOSIUM, Digest of Technical Papers, 1987, pp. 79-80. In the DRAM proposed by Watanabe et al., there is further provided a BiCMOS differential sense amplifier between the write data bus and each bit line pair, separately from the conventional flip-flop type sense amplifier.
FIG. 5 is a diagram showing a circuit structure of the DRAM disclosed by Watanabe et al. in the above described prior art document.
In FIG. 5, write data buses IL and IL and read data buses OL and OL are separately provided on both sides of a bit line pair BL and BL. In a read mode, the bit lines BL and BL are isolated from the write data buses IL and IL in response to a signal WRITE. There is provided a BiCMOS differential sense amplifier DS1 between the read data buses OL and OL and the bit line pair BL and BL. An input stage of the BiCMOS differential sense amplifier DS1 is connected to the bit lines BL and BL through a clocked inverter CI. Between the read data buses OL and OL and a data output buffer DB, there are provided a level shifting circuit LS for shifting signal voltage levels on the read data buses OL and OL and another BiCMOS differential sense amplifier DS2 for differentially amplifying an output of the level shifting circuit LS to apply the same to the data output buffer DB.
The write data buses IL and IL are respectively connected to the bit line BL and the complementary bit line BL. Similarly, the read data buses OL and OL receive data from the bit line BL and the complementary bit line BL through the BiCMOS differential sense amplifier DS1. In FIG. 5, signals CSL1 and CLS2 indicate column decoded signals from a column decoder (not shown).
FIG. 6 is a waveform diagram showing potentials of main nodes in a reading operation of the DRAM shown in FIG. 5. Referring to FIG. 6, description is made of an operation to occur when a memory cell MC storing data "0" is selected, to be connected to the bit line BL.
At the time of reading, the signal WRITE becomes a low level, so that all the bit lines BL and BL are isolated from the write data buses IL and IL. First, the word line WL is selected in response to an externally applied row address signal, to be activated. Thereafter, data stored in memory cells MC connected to the selected word line WL are transferred to the corresponding bit lines BL, resulting in, a small change in voltage on the bit lines BL depending on the data. This small change in the bit line voltage causes conductance modulation of a CMOS clocked inverter CI. This conductance modulation is applied to the input stage of the BiCMOS differential sense amplifier DS1 in response to the column decoded signal CSL1. The BiCMOS differential sense amplifier DS1 has been already activated by the signal CSL1, to amplify the small signal in a short time period by its high current drivability. Data on the bit line pair BL and BL are transferred to the read data buses OL and OL. Signal voltages on the read data buses OL and OL are shifted in level and amplified by the level shifting circuit LS and the other BiCMOS differential sense amplifier DS2. The amplified data RD are applied to the data output buffer DB, to be outputted. At the same time, a conventional flip-flop type sense amplifier FS is activated, so that data stored in memory cells are restored. Thus, before or simultaneously with activation of the conventional flip-flop type sense amplifier FS, the data stored in the selected memory cell MC is read out, resulting in high-speed reading.
At the time of writing, the signal WRITE becomes a high level, so that data writing is performed through the write data buses IL and IL in the same manner as that in the conventional DRAM shown in FIG. 3.
In this prior art, however, each of the bit lines BL and BL is not directly connected to the input stage of the BiCMOS differential sense amplifier DS1 but indirectly connected thereto through the clocked inverter CI. The clocked inverter CI generally has a circuit structure shown in FIG. 7. This clocked inverter comprises a CMOS inverter formed of a PMOS load transistor Q.sub.PL and an NMOS driver transistor Q.sub.ND connected in a complementary manner, and cut-off switching transistors Q.sub.PC and Q.sub.NC respectively connected to a power-supply potential Vc and a ground potential. The cut-off switching transistors Q.sub.PC and Q.sub.NC inhibit an operation of an inverter, i.e., inversion of an input IN to an output OUT when a control clock CLOCK is at a low level and a complementary signal CLOCK is at a high level. On the other hand, the clocked inverter functions as an ordinary inverter when the control clock CLOCK becomes a high level.
One reason why the prior art employs the clocked inverter in addition to the BiCMOS differential sense amplifier is that an input impedance of a bipolar transistor is in general substantially lower than that of a MOS transistor. Therefore, in order to avoid adversely affecting a bit line voltage and an amplifying operation of a CMOS flip-flop type sense amplifier, an isolating device is required. Another reason is for supplying a base current to the bipolar transistors in the BiCMOS differential sense amplifier and for amplifying the input amplitude of the differential sense amplifier.
As described in the foregoing, the prior art has a disadvantage in a high-speed reading operation because clocked inverters are required and the reading operation is inherently delayed by the clocked inverters.
Furthermore, the prior art has another disadvantage in view of the occupied area in achieving larger scale integration because each of the clocked inverters comprises at least four transistors.
Additionally, the differential sense amplifier of the prior art is not sufficient for a high-speed operation because it does not have positive feedback for accelerating the amplification of an input voltage to supply an output voltage.